High speed computer application specific integrated circuit

ABSTRACT

An integrated circuit chip for application in a computer for performing  h speed arithmetic operations in hardware has hardware for forming a system clock processor circuit, a timer circuit, a program counter and branching circuit; an interrupt processor circuit formed in the chip; an interrupt address random access memory, mathematical computation circuitry and an internal data random access memory. The mathematical computation circuitry includes a circuit for performing combined division and square root operations. The integrated circuit operates on a fixed instruction set and provides the means for performing instruction and operand look-ahead to permit execution of each instruction in a single clock cycle.

BACKGROUND OF THE INVENTION

This invention relates generally to high speed computer processingcircuitry and particularly to high speed microcomputer circuitry thathas low power consumption, provides powerful mathematical processing andwhich may be programmed with a high level language structure at theassembly code level. Still more particularly, this invention relates toan application specific integrated circuit that may be included in acomputer system.

The previous method of achieving high speed operation in a processor isby microprogramming very primitive instruction fields. In suchprocessors the execution of interrupts and branching instructions alwaystakes more than one clock cycle. The software design effort anddifficulty level increases if the instruction set is made up ofprimitive commands. In the order of programming ease, the high-levellanguage is the preferred choice, followed by assembly language, thereduced instruction set computer (RISC) instructions, and themicroprogram language.

Prior art processors do not perform divide and square root operations inhardware. The prior art processors accomplish division calculations withsoftware, which is time consuming. Conventional microprocessor accesslook up tables or software codes for square root calculations, which isalso time-consuming.

SUMMARY OF THE INVENTION

The invention provides a microcomputer with the desirablecharacteristics of small size, fast throughout rate, low powerconsumption, powerful mathematical processing, and high level languagestructure at the assembly code level. The microcomputer is formed as ahigh speed computer application specific integrated circuit.

The microcomputer according to the present invention creates a highlevel language format by building in an instruction decoded to generatethe microprogram control fields. This unique design provides a highlevel language environment, maximum speed, and single instructionexecution per instruction cycle. Single-clock instruction execution,including branching and interrupt, improves processor speed. This typeof execution is an improvement over all microprocessors that requireseveral clock cycles to execute an instruction. The processor accordingto the present invention combines instruction look ahead and the correctpipeline length, it only needs one clock cycle to perform branching andprocess interrupt requests.

The present invention uses a harvard architecture processor implementedwith the best features of reduced instruction set computer (RISC) andcomplex instruction set computer (CISC) machines. The processor isdesigned for high speed data manipulation and branching with a simplebut powerful instruction set. The Harvard architecture separates theinstruction and data buses to eliminate the bus bottleneck problem ofall single bus microprocessors. The present invention has one programbus for instruction and three data buses for data. The buses allowparallel operation to increase execution speed. The present inventionprovides a fixed instruction-set machine that has the programminglanguage environment of a CISC and the execution speed of a RISC. Theinstruction used in the present invention set is similar to the BASIClanguage, which is an improvement over the assembly language environmentof all microprocessors (CISC machines), the simple instruction setenvironment of RISC machines that require multiple instruction to do aCISC command, and the bit-level manipulation of microprogrammedprocessors.

The ASIC incorporates the necessary internal circuitry to execute thefollowing mathematical operations in hardware: multiplication, division,and square root calculation. The present invention preferably provides16×16 bit multiplication, which produces a 32 bit output; division of a32 bit numerator by a 16 bit denominator; 16-bit radicand square rootcalculation; a 16 bit arithmetic logical unit (ALU); and a 32 bit barrelshifter. This hardware implementation of mathematical operations allowsthe execution of mathematical functions with corresponding softwareinstructions rather than constructing a software algorithm. The hardwareexecution of mathematical functions is much faster than softwarealgorithms.

The processor according to the present invention has several advantagesover conventional microprocessors. The invention has an instruction setthat is a high level language format and can execute mathematicalequations much faster than conventional microprocessors. The division,square root and multiplication speeds of the conventional microprocessorare also severely limited by software implementation of the complexmathematical instructions. The more powerful mathematical capability ofthe present invention allows for the implementation of complex functionsat significantly higher speed.

The present invention has a much more advanced interrupt processor andtimer section than a conventional microprocessor or microcomputer. Theinterrupt processor can accommodate 23 separate external interrupts. Theinterrupt processor preferably contains two 12-bit mask registers toindividually mask each interrupt input or globally disable all interruptinputs. The interrupt processor works on a queue system. The interruptprocessor assigns a unique priority to each interrupt so that no twointerrupts have the same priority. The present invention contains adedicated internal interrupt address RAM. This internal interruptaddress RAM is user programmable and contains the addresses of the firstinstruction for each of the 23 interrupt service routines.

The timer section of the HSC ASIC consists of six 16-bit up counters andsix 16-bit threshold latches. Each up counter (timer) is paired with athreshold latch. The data outputs of each timer/latch pair are comparedwith a dedicated digital comparator. The output of the comparator isasserted if the timer value is greater than or equal to thecorresponding latch value. The comparator outputs are connected tooutput pins of the SIC for system use.

The timers are controlled by a 6-bit timer control register and thetimers are clocked by a separate clock input to the HSC ASIC. All of thetimers, threshold latches, and timer control register are mapped intothe source and destination address space of the HSC ASIC; therefore,each of them can be written to or read from.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a pin diagram of an application specific integrated circuitaccording to the present invention;

FIG. 2 is a block diagram showing connections between the basiccomponents that comprise the ASIC of FIG. 1;

FIG. 3 illustrates mathematical computational components that may beincluded in the circuit of FIG. 2; and

FIG. 4 illustrates combined square root and divider circuits that may beincluded in the circuit of FIG. 2.

FIG. 5 illustrates the logical relationship between a timer latch pairthat may be included in the circuit of FIG. 2;

FIG. 6 is a generalized block diagram of an interrupt processor that maybe included in the circuit of FIG. 2; and

FIG. 7 is a timing diagram for the application specific integratedcircuit of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 illustrates a functional pin arrangement for a microprocessorapplication specific integrated circuit (ASIC) 20 according to thepresent invention. The ASIC 20 includes a RESET terminal 21 forreceiving a rest signal that is asserted upon system power-up for timesgreater than or equal to six system clock (clock in) periods. The resetsignal initiates various reset functions within the ASIC 20 as describedsubsequently. The ASIC 20 receives data inputs from external datasources, (RAM and ROM) and sends data outputs to the external RAM, andother external data processing circuitry.

The software is interrupt-driven. In a preferred embodiment, the ASIC 20has-twenty three separate interrupt inputs that may be input to anINTERRUPT terminal 22. These interrupts preferably are edge-activatedand asserted high. In the preferred embodiment, an external source (notshown) requesting an interrupt must keep the interrupt signal inputasserted for a minimum of 1.5 Clock In periods.

The ASIC 20 has a CLOCK IN terminal 23 that provides an input for aclock signal that will be processed by an internal system clockprocessor 33 shown in FIG. 2. The output from this system clockprocessor 33 will clock a program counter 34, also shown in FIG. 2, anddetermine the rate at which instructions will be executed. The frequencyof CLOCK IN signals should be two times the desired rate at which thefastest instructions will be executed.

Referring again to FIG. 1, the output of the program counter 34 appearsat a PC output terminal 24 for driving the address ports of an externalprogram programmable read-only memory (PROM) 36. The PROM 36 isconnected to a terminal 38 of the ASIC 20 via a program word bus, whichcontains the two source-operand addresses, the destination address andthe opcode for the instruction set.

The ASIC 20 has a TIMER CLK terminal 25 that receives timer clocksignals for driving internal timer clock inputs. The ASIC 20 furtherincludes 6 TIMER INTERRUPT terminals 26. The timer interrupt signals areoutputs from individual timers (not shown) included in the ASIC 20. Alatch corresponds to each timer. Each interrupt output will be assertedwhen the value of the timer is greater than or equal to the value in thecorresponding latch.

An address bus terminal 27 is connected to a multiplexed address busAX/AZL2 that provides the destination address for the computed resultand the source address for the X operand on alternate cycles of CLOCK INsignals.

The ASIC 20 has has an output terminal 28 for providing output writeenable signals WE(L) that may be used to drive the write enable input ofexternal random access memories (not shown). The write enable signalsare asserted low. A WE(L) signal is output during a portion of the timewhen the destination address is on the AX/AZL2 address bus.

Still referring to FIG. 1, a terminal 29 is connected to a data bus DX,which provides means for inputting data for one of two source operandsfor an arithmetic instruction. The data bus DX preferably is a 16 bitdata bus.

A terminal 30 is connected to an output data bus DZL1 that contains theresult of an arithmetic operation performed by the ASIC 20.

An output terminal 31 provides a SNEW signal whose period is equal tothe instantaneous execution rate of the ASIC 20. The fastestinstructions can be executed at one-half the frequency of the CLOCK INsignals. Slower instructions, such as divide and square root, willrequire multiple cycles of the CLOCK IN signals. The internal circuitryof the ASIC 20 will be clocked at less than one-half the frequency ofCLOCK IN to accommodate slow instructions. These slow instructions causethe SNEW signal to become in integral submultiple of the CLOCK INfrequency. The SNEW signal is internally generated to clock the programcounter 34. Externally, the SNEW signal serves as an indication of theactual execution of the instruction. Each cycle of the SNEW signalindicates that another instruction is being executed.

Referring to FIG. 2, the ASIC 20 can be internally subdivided into thefollowing subunits: the system clock processor 33, the program counterand branching circuitry 34; an internal bus structure; mathematicalcomputation circuitry and multiplexing circuitry 40; a timer andcomparator block 42; an interrupt processor 44; an interrupt address RAM46 and an internal data RAM 48. FIG. 2 shows these subunits and theirinterrelationships in a general block diagram of the ASIC 20.

The system clock processor 33 provides signals to the program counterand branching circuitry 34, the mathematical computation circuitry andmultiplexing circuitry 40, the timer and comparator block 42, theinterrupt processor 44, interrupt address RAM 46 and the internal dataRAM 48.

The mathematical computation circuitry and multiplexing circuitry 40receives signals from the system clock processor 33, the program PROM36, the timer and comparator block 42, the internal data RAM 48 andexternal RAM and ROM (not shown). The mathematical computation circuitryand multiplexing circuitry 40 provides signals to the program counterand branching circuitry 34, the timer and comparator block 42, theinterrupt processor 44, the interrupt address RAM 46, the internal dataRAM 48 and the external RAM and ROM.

The frequency of the internal system clock (CLK 1) will be as close to10 MHz as possible. An internal clock processor will use one externalclock signal to generate a two-phase, non-overlapping clock signals.This pair of clock signals is referred to as CLK1 and CLK1. CLK1 andCLK1 are always one-half the frequency of CLOCK IN. CLOCK IN alsogenerates two internal clock signals called PH₋₋ A and PH₋₋ B, whichhave the same frequency as CLOCK IN, and clock all of the computer'sinternal latches. PH₋₋ A has the same phase as CLOCK IN, and PH₋₋ B isthe inverse of PH_(--A).

The system clock processor 33 receivers the CLOCK IN, TIMER CLOCK andRESET signals. Two external digital clock signals (CLOCK IN and TIMERCLK) are required for operation of the microprocessor 20. These signalsare input to the system clock processor 33 as shown in FIG. 2.

The TIMER CLK has a much lower frequency than CLOCK IN. The timer clockmay be asynchronous to the system clock since synchronization takesplace internally. The period of the timer clock should be greater than16 CLOCK IN periods or 8 CLK1 periods with a high time of more than 6CLK1 periods or 12 CLOCK IN periods.

The ASIC 20 preferably has four internal data buses and five internaladdress buses. The four data buses are referred to herein as DX, DY, DZand DZL1. The data buses DX and DY are used as source-operand databuses. DZ is the data bus that contains the result of a computationaloperation upon the DX and DY data. The data bus DZL1 is a latchedversion of DZ that appears one clock cycle after DZ. It is 16 bits wideand appears at the I/O pads of the ASIC 20.

The internal address buses are referred to herein as AX, AY, AXL1,AX/AZL2, and AY/AZL2. The address buses AX and AY contain either theaddresses of the source operands or the data for computations. AZL1contains the destination address of the data on DZ.

AZL1 appears one clock cycle later in time than AX and AY. This isindicated by the "L1" in the acronym AZL1. AZL2 is a latched version ofAZL1 that appears one clock cycle after AZL1. AZL2 and AX aremultiplexed during each clock cycle and sent off chip to externalcomponents on a 16-bit address bus referred to as AX/AZL2.

The AY/AXZL2 address bus is handled in a manner similar to thatdescribed above for the AX/AZL2 address bus. The AY/AXZL2 address bus is8 bits wide, but it is connected only to the internal data RAM 48.

During the positive phase of CLK1, AZL2 appears on the AX/AZL2 and theAY/AZL2 address buses and contains the destination address of the dataon DZL1. During the negative phase of CLK1, AX appears on the AX/AZL2bus and AY appears on the AY/AZL2 bus. AX and AY serve as sourceaddresses for the data that will appear on the DX and DY data buses

An internal, 16-bit bus is routed throughout the ASIC 20 connecting theoutputs of certain circuits. An example of an output connected to thereadability bus is shown in FIG. 5. It is desirable to read certainvalues in the computer that are normally not available to theprogrammer. This capability is accomplished by connecting these outputsonto a tristate bus designated as the "readability bus," whichterminates as one of the inputs to the X operand multiplexer. Thereadability bus will supply the current value of these outputs as an Xoperand to the following listed components when they are properlyaddressed:

a. Timers

b. Threshold latches

c. Mask registers

d. Top of interrupt processor status stack and status flags

e. Output of interrupt address RAM

f. Top of program stack

g. Timer mode register

h. Divider remainder

The system clock processor 33 provides TIMER CLK, CLK1, RESET, PH₋₋ Aand PH₋₋ B signals to the timer and comparator block 42. The timer andcomparator block 42 also receives inputs from the mathematicalcomputation circuitry and multiplexing circuitry 40 via the AX operandaddress bus and the AX/AZL2 address bus. The timer and comparator block42 receives a timer/latch value from the mathematical computationcircuitry and multiplexing circuitry 40. The timer and comparator block42 also send the TIMER INTERRUPT signals to an external source (notshown).

An output of the timer and comparator circuits 42 is a latch/time outputsignal that is input to the mathematical computation circuitry andmultiplexing circuitry 40.

The program counter 34 of the ASIC 20 generates a new 13-bit address forthe external program PROM 36 at the beginning of each instruction cycle.The program PROM 36 returns a 48-bit program word to the ASIC 20.

Still referring to FIG. 2, in response to an external interrupt inputthe interrupt processor 44 generates an interrupt vector. A separateinterrupt vector is generated for each interrupt. The interrupt vectorsare sent to the address ports of the interrupt address RAM 46. Theinternal interrupt address RAM contains the address for the interruptservice routine associated with the interrupt vector.

The interrupt address for a particular interrupt service routine isloaded from the interrupt address RAM 46 into program counter 34. Theinterrupt address look-up RAM must be loaded with the proper interruptaddresses as part of the initializing software following power-up.

The program counter 34 preferably is a 13-bit register that changes itsoutput value unconditionally upon every clock cycle. It is clocked bythe SNEW signal. The program counter 34 instigates every branchingdecision and computation in the ASIC 20.

The 13-bit program counter output signal from the ASIC 20 becomes theaddress of the program PROM 36. The program word located at a particularaddress in the program PROM 36 is sent back to the ASIC 20 forexecution. The 13 bits give the program counter and branching circuitry34 the capability to address 2E13 (8,192) words of program PROM 36.

In the absence of a branching instruction or interrupt, the programcounter and branching circuitry 34 output is sequential. Upon occurrenceof a branch instruction or interrupt, the program counter and branchingcircuitry 34 is loaded with a non-sequential value. This value becomesthe address of a subroutine or an interrupt service routine locatedsomewhere in the program PROM 36.

There are four types of branching instructions:

a. Calls

b. Jumps

c. Return from subroutines

d. Return from interrupts (RETI)

Each type of branch instruction has six variations:

a. =0

b. 0

c. <0

d. ≧0

e. Overflow

f. Unconditional

The four types of branching, with six variations of each type, result in6×4=24 branching combinations.

Upon a call to a subroutine, the return address is first stored on a 64word deep program status stack (not shown). If errant software causesthe program stack pointer to overflow or underflow, an internal trapfunction causes a trap vector stored in the interrupt address RAM 46 tobe loaded into the program counter and branching circuitry 34 on thenext instruction cycle. The trap vector is user programmable.

the conditional branching is dependent upon three status bits from thecomputational circuitry of the microprocessor 20:

a. ≠0 or =0

b. <0 or ≧0

c. Overflow

If the requirements of a conditional branch instruction are met or anunconditional branch instruction is executed, the new program address isloaded into the program counter and branching circuitry 34 for theinstruction immediately following the branch instruction. There are nopipeline breaks caused by branch instructions.

Both the top of the program stack and the latest values of the statusbits are addressable and available as X operands to the internal datamathematical computation circuitry and multiplexing circuitry 40.

The mathematical computation circuitry and multiplexing circuitry 40includes multiplication, division, square-root calculation, barrelshifting, Boolean operations, addition, and subtraction.

The ASIC 20 preferably contains an on-board, 16×16-bit multiplier (notshown) that is capable of four-quadrant multiplication. Both of itsoperands must be in twos complement form, which gives a 32-bit result.However, overflow circuitry following the multiplier will indicateoverflow for results greater than 16 bits. This overflow indicationgives the software programmer the ability to make a conditional branchto a scaling subroutine. The greater-than-16-bit multiplier result canbe scaled by the divider or barrel shifter such that a smaller 16-bitresult on the DZ data bus can be stored in the internal data RAM 48.

Any multiply instruction will result in latching all 32 bits of themultiplier output and making the least significant half (LSH) of themultiplier output available to all components of the mathematicalcomputation circuitry (square root, divider, barrel shifter, ALU, andmultiplier). However, the most significant half (MSH) of the latchedmultiplier output is available to only the divider and the barrelshifter. The multiplier output is commonly called the product register.The MSH of the product register can be independently loaded with a valuefrom the 16-bit DZ data bus. This feature enables the programmer toeasily load the product register with a specific bit pattern.

The mathematical computation circuitry 68 that my be included in theASIC 20 is represented in block diagram form in FIG. 3. The dividedcircuit 74 will operate on a 32-bit dividened (numerator) and a 16-bitdivisor (denominator) and give a 16-bit quotient with a 16-bitremainder. The remainder is used to round up the quotient if it is ofsufficient magnitude.

The X and Y-operands are input to a D-type flip-flop 70, which alsoreceives the timing signal SNEW from the system clock processor 33. TheX and Y-operands are input to an arithmetic logic unit (ALU) 72. Anarithmetic programmable logic array 71 receives an OP CODE signal fromthe program PROM 36 and outputs a signal to the ALU 72 indicatingwhether to perform addition, subtraction, or a Boolean operation. The Xand Y-operands are also input to a multiplier 73, which provides themost significant half of the X-operand to the divider 74. The Y-operandand the least significant half of the X-operand are separately input tothe divider 74.

The divider 74 is capable of four-quadrant division of a 32-bit dividendby a 16-bit divisor. The result is a 16-bit quotient and a 16-bitremainder. The divider 74 preferably automatically rounds up thequotient. If the remainder is greater than half of the divisor, thequotient will be incremented. The quotient is available on the DZ andDZL1 data buses, and the remainder is accessible to the programmer viathe readability bus. The circuitry is designed to calculate X/Y or Y/Xaccording to the programmer's needs.

The divider 74 outputs the quotient to a multiplexer 76 and outputs anoverflow bit to a multiplexer 78. Even through the X operand is only 16bits, the divider has the capability for a 32-bit dividend. If themultiplier operates on two inputs whose magnitudes are of sufficientquantity such that their product requires greater than 16 bits, thesoftware programmer can detect this situation by monitoring themultiplier OVF bit. If the OVF bit is set, all 32 bits of the multipliermay be scaled by an integer number with the divider such that the resultcan be represented in only 16 bits.

The divider 74 preferably is an unclocked array of adder/subtracterelements. This type of design has a speed advantage over clocked,state-machine-type designs. To further increase speed, the design ispreferably based on a non-restoring, binary division algorithm. Anon-restoring algorithm is faster than a restoring algorithm, but itrequires much more physical area to implement.

FIG. 3 also includes a square root extractor 80. The square rootextractor 80 will operate only on the 16-bit X operand from the outputof the flip flop 70. The square root extractor 80 will calculate an8-bit integer square root with an 8-bit remainder. If the remainder isof sufficient magnitude, the square root will be rounded up.

For instance, SQRT (81)=9 RO and SQRT (100)=10 RO, and the answers willbe given as 9 and 10 respectively. The SQRT (90) is 9R9=9.49. In thiscase, the answer will be given as 9 since the remainder was equal to orless than the integer square root. However, SQRT (91)=9R10=9.54, and theanswer will be given as 9+1=10. In the second case the integer squareroot was incremented because the remainder was greater than the integersquare root.

The X operand is an integer, twos complement number. The square rootextractor 80 will give correct answers for positive radicands only;however, it recognizes negative, tows complement numbers and will setthe overflow bit (OVF) on detection of such numbers.

The square root circuit design is also based on an unclocked array anduses a non-restoring type algorithm. The algorithm for square rootextraction requires a multiplexer for each add/substract element in theunclocked array.

The dividend, divisor, and quotient are two complement, binary numbers.The dividend and divisor will be integers. Their binary points will beto the right of their least significant bits (LSBs).

the underlying principle of operation of the divider 74 and the squareroot extractor 80 is non-restoring binary division. The divider 74 has acorrection circuit that will correct the sign of the quotient for allsign combinations of the dividend and divisor. The divider 74 may berealized with sixteen, 16-bit adder/substracter stages (not shown). Thefirst fifteen stages derive the quotient and remainder bits, and thelast stage corrects for sign.

The divider 74 has the ability to detect quotient overflow resultingfrom maximum negative quotient, division by zero, or maximum negativedividend. Positive overflow is also detected if the resulting quotientis too large to be represented by a 16-bit, twos complement number.

The ALU 72 provides Boolean arithmetic, addition and subtractioncapability. Both inputs to the ALU 72 preferably are 16 bits. Forarithmetic operations, the inputs must be twos complement. The ALU 72 iscapable of generating an overflow output for all operations exceptBoolean operations.

Referring still to FIG. 3, the mathematical computation circuitry 68preferably contains a barrel shifter 82 of limited capability. Thebarrel shifter 82 receives the Y-operand and the MSH and LSH of theX-operand. The barrel shifter 82 provides an overflow output to themultiplexer 78 and a Q output to the multiplexer 76.

The barrel shifter 82 can do a logical right shift on a 32-bit operand.The amount of bits to be shifted is determined by the software and canbe from 0 to 16 bits in a signal instruction cycle. The 32-bit operandcan be positive or negative. The AX bus contains (or points to) the16-bit operand. The AY bus value indicates the number of bits the 16-bitoperand is to be shifted right. The barrel shifter provides an overflowoutput that will be a helpful to the programmer in determining if themagnitude of the right shift operation is large enough for the numeratorinvolved. The overflow output will signify quotient overflow. The numberof bits right-shifted is actually a denominator that characteristicallyhas a positive power of 2. The 32-bit numerator could be a large enoughmagnitude, and the denominator could be small enough, such that the16-bit quotient would not contain all of the MSBs in the originalnumerator. The only way the barrel shifter overflow will be asserted iswhen the operand is from the 32-bit product register. If the operand isfrom the 16-bit data bus, the OVF will never be generated, regardless ofthe number of right shifts.

FIG. 4 is the block diagram of the combined square root 80 and dividercircuit 74 that is actually implemented in the ASIC 20. The dividend isinput to a dividend absolute value circuit 102. The most significant bitof the dividend is input to an abort logic circuit 104. The absolutevalue of the dividend is input to a multiplexer 106, which directs theabsolute value to the dividend to a divide and square root array 108.The divide and square root array 108 contains necessary adders (notshown) and multiplexers (not shown) for doing division or square rootcalculations in a shared circuit. The divisor is input to a multiplexer110, which provides the divisor to the divide and square root array 108.

When doing division, the divide and square root array 108 outputssignals to a divide quotient correction circuit 112 and to a divideremainder correction circuit 114. The divide remainder is input to asubtraction circuit 118 that subtracts the absolute value to the divisorfrom the absolute value to twice the remainder. The output of thecircuit 118 is input to the divide quotient roundup circuit 16. The mostsignificant bit of the divide quotient correction is provided to theabort logic circuit 104. The divide quotient is input to a dividequotient roundup circuit 116, which produces the quotient and directsthe most significant bit of the divide quotient and its sign bits to theabort logic circuit 104.

When performing square root calculations that combined square root anddivider circuit 110 receives the radicand in the multiplexer 106. Aninstruction SQRT(H) from external control circuitry (not shown) is inputto the multiplexer 106 and to the abort logic circuit 104. The abortlogic 104 monitors signals throughout the combined square root anddivider circuit 100 for both division and square roots and asserts theoverflow signal is necessary.

The output of the divide and square root array 108 is directed to asquare root remainder correction circuit 120 and to a square rootroundup circuit 122. The remainder correction is combined with theoutput to the divide and square root array 108 in the square rootroundup circuit to produce the square root result.

The combined square root and divider circuit 100 will process a 16-bitradicand yielding an 8-bit square root) or a 32-bit dividend and a16-bit divisor (yielding a 16-bit quotient with an 16-bit remainder).The 16-bit radicand must be packed with zeros such that it is convertedto a 32-bit number having an MSB=0, 16-bits of radicand and 15 LSBs=0.This zero packing is necessary so that the radicand and dividend canshare the same circuitry in the divide and square root array 108. Thezero packing is done inside the ASIC.

The computation circuit provides status bits that describe themathematical computation of the current clock cycle. These status bitsare:

a. ≠0, =0

b. ≧0, <0

c. overflow (OVF)

These status bits are latched at the end of every arithmetic instructionand sent to the branching circuitry. Latching the status flags allowsmultiple, successive branch instructions that refer to the same statusflag generated by the last computational instruction. When the lastarithmetic instruction was a multiply, the latched status bits are validfor the complete 32-bit output of the multiplier.

Each of the two operands (X & Y) for the multiplier, divider,square-root extractor, barrel shifter, and ALU can come from varioussources. The 16-bit X operand can be source from AX, DX, DZ, thereadability bus, or the fed-back output of the multiplier. The 16-bit Yoperand can be sourced from AY, DY, or DZ. The choice of the X and Ysource operand is selected by a multiplexer located in front of themultiplier, divider, ALU, barrel shifter, and square root extractor. Theoutput of the multiplexer is clocked into the D-type register 70.

The timer section timer and comparator block (42) preferably includessix digital timers, six storage latches, a 6-bit control register, andsix digital comparators. The logical relationship among these componentsfor one timer is illustrated in FIG. 5.

The destination address and CLK 1 signals are input to a destinationaddress decoder 132. The destination address decoder 132 provides anenable signal to the enable terminals of a control latch 134 and a timer136. The destination address decoder also provides enable signals tofive other timer enable inputs (not shown) and to five other latchenable inputs (not shown). These other timers and latches are identicalto the timer 136 and the latch 134.

The timer 136 is controlled by one bit of the control register or latch134. The timer 136 receives a TIMER₋₋ CLK signal from the system clockprocessor 33 of FIG. 2. If the control bit from the latch 134 is a "1",the timer 136 will count up with each cycle to TIMER₋₋ CLK. The signalTIMER₋₋ CLK is derived from the TIMER CLOCK input to the system clockprocessor FIG. 2 and is synchronized with Ph₋₋ A, Ph₋₋ B, and CLK 1. Ifa bit in the control register is a "0", the timer will stay reset.

The output of the the destination address decoder 132 is also input to astorage latch 138. The storage latch 138 is programmed with a thresholdvalue that is continuously compared by a comparator 140 with the outputof the digital timer 136. If the timer value of a timer 136/latch 138pair is greater than or equal to the corresponding latch 138, the outputof the comparator 140 will be asserted high. The output of thecomparator 140 is applied to a transparent latch 142, which alsoreceives the CLK 1 input at its enable terminal. The transparent latch142 allows its input data to propagate to the output when the CLK 1input at its enable terminal input is HIGH.

The output of the timer 136 is input to a tri-state driver circuit 146for the readability bus.

A source address decoder 144 decodes a source address signal andgenerates one enable signal for the tri-state driver circuit 146 or forthe tristate drivers for the five other timer outputs or the five othercontrol latch outputs.

In the timer and comparator block 42 six digital comparators compare sixtimer/latch pairs. The comparators always reflect the relative valuebetween the timer and latch. If a timer value is larger than the latchvalue, the comparator output will be asserted. However, if the latch ofthe same timer/latch pair is programmed with a value higher than thepresent timer value, the comparator output will become deasserted. Eachtimer and corresponding threshold latch is 16 bits wide. The timercontrol register is 6 bits wide, one bit for each of six timers.

FIG. 5 is a logical representation of the timer section, but does notreflect the actual physical implementation. The actual timer and latchvalues are stored in a small random access memory (RAM) and periodicallyrecalled for comparison and timer incrementing.

It was desired that the timer section be highly visible to theprogrammer. To achieve this visibility, the timer section wasextensively memory-mapped. All six threshold latches, all six timers,and the control register are programmable. Additionally each of theiroutputs in readable and visible on the external data bus. Theprogrammability and readability functions are under program control.

Each of the values is read by providing the proper source address to thesource address decoder 144 of FIG. 5. The output of the source addressdecoder 144 will then enable the proper tristate driver. To program acertain register, the proper address must be applied to the destinationaddress decoder and the desired data applied to the data bus. The outputof the destination address decoder will enable the proper component toaccept the data.

The internal data RAM 48 in the ASIC 20 is preferably an internal 256word×16 bit, dual-port RAM. Referring to FIG. 2, the two address portsare connected to the AX/AZL2 and AY/AZL2 address buses. The outputs ofthe internal data RAM 48 are connected to the DX(NT) and DY data buses.Data from the DZL1 bus is written to the input port of the RAM.

The microprocessor 20 provides for RAM expansion by routing the AX/AZL2address and DX, and DZL1 data buses to I/O pads.

Referring to FIGS. 2 and 6, each interrupt signal has a differentpriority within the interrupt processor 44. Each interrupt input can bemasked by the computer program. When conditions are correct, theinterrupt processor 44 will send an interrupt request to the programcounter and branching circuitry 34. The interrupt address RAM 46 ispreferably an internal, 13-bit by 24 word RAM. Each interrupt isassociated with a unique 5-bit interrupt vector. This 5-bit vector isdecoded by the interrupt address RAM 46 to yield the starting addressfor the interrupt service routine. The interrupt address RAM 46 can beprogrammed with 23 unique interrupt-routine addresses by the computerprogram. The interrupt address RAM 46 also contains a trap address whichis also user programmable. This address is loaded into the programcounter and branching circuitry 34 is any of the two stacks in the ASIC20 under flow or overflow.

When an interrupt service routine is finished, the program counter andbranching circuitry 34 must indicate completion to the interruptprocessor 44 by asserting the return-from-interrupt (RETI) signal.

Some software instructions in the program cannot be interrupted. Amongthese are branch instructions. The most significant bit (MSB) of the48-bit instruction word is asserted if that instruction is not to beinterrupted. This interrupt inhibit bit goes to the interrupt processor44 to inhibit interrupt requests for one clock (CLK 1) cycle.

A general block diagram of the interrupt processor 44 is shown in FIG.6. The interrupt processor 44 can be subdivided into an interrupt datapath 200 and an interrupt stack control 202.

Most of the signal I/O lines of the interrupt processor 44 are sourcedfrom or destined for other parts of the ASIC 20 circuitry. However, somesignal paths between the sections of the interrupt processor or fromoutside the ASIC are present.

The only signals the interrupt processor 44 receives from a sourceexternal to the ASIC 20 are the actual interrupt signals. The 23separate interrupt inputs are synchronized with the clocking regime bymeans of an internal synchronizer 204.

DZL1 is part of the 16-bit data bus within the ASIC 20 and will carrydata to be loaded into two mask registers (not shown) contained withinthe interrupt data path 200. DZL1 also is used to load the interruptaddress RAM 46 with the interrupt service-routine addresses. Theinterrupt address RAM is addressed by AZL2.

When interrupts are received, the interrupt address RAM 46 depicted inFIG. 2, will eventually output the address of the first instruction forthe associated service routine located in the program PROM 36 assuming ahigher priority interrupt is not currently executing. These addresseswill be loaded into the program counter and branching circuitry 34.

The interrupt processor 44 can process a total of 23 externalinterrupts. The external interrupt input pulse width must be ≧1.5periods of CLOCK IN. All 23 external-interrupt inputs are edge-activatedby the low-to-high transition of a pulse. Once an interrupt has beenprocessed, it will not be recognized again by the ASIC 20 until anotherlow-to-high transition of the interrupt input.

If an interrupt input becomes asserted and is not masked out by the maskregisters, a corresponding bit with a 23-bit storage register (notshown) will be set. This bit will remain set until the correspondinginterrupt-service routine is completed by the ASIC 20. If the externalinterrupt signal becomes inactive before the corresponding interruptservice routine is executed (because a higher priority interrupt isbeing executed), the ASIC 20 will "remember" to execute the routinebecause the bit within the storage register is set. A return tointerrupt signal (RETI) within the interrupt software routine will clearthe bit.

The external interrupt inputs may be generated asynchronously with thesystem clock input. The internal interrupt processor 44 will synchronizethe interrupt inputs. The synchronizers may include three latchesconnected in series. Each latch is clocked with an alternate phase ofthe clock.

The interrupt processor 44 includes a priority encoder that generates a5-bit code that is dependent upon the bit pattern of the 23 inputs. This5-bit code is the interrupt vector. The priority encoder is programmedto recognize which of the 23 inputs has the highest priority and tooutput an interrupt vector unique to the highest priority input that ispresently asserted. Each interrupt input is internally assigned anindividual priority ranging from 1 to 23, with 1 being the highestpriority.

As shown in FIG. 2, this 5-bit interrupt vector addresses the internalinterrupt address decoding RAM 46. The 13-bit interrupt address RAM 46output is the address of the interrupt software service routine locatedin the program PROM 36. The interrupt processor works on a queue system.If an interrupt occurs, and no other interrupt of higher prioritycurrently is being serviced by the software, the interrupt will resultin an interrupt request being sent to the branch control logic;otherwise that interrupt must wait in the queue.

To accomplish the queueing system, the interrupt processor 44 has aninterrupt status stack (not shown) that operates under the control ofthe interrupt stack control 202. This stack contains the lower priorityinterrupt vectors that have been interrupted by interrupts of higherpriority. The stack holds the interrupt vectors of the lower priorityinterrupts until the higher priority interrupt service routines arefinished.

If an external interrupt becomes asserted and its priority happens to behigher than the priority of the interrupt service routine, that thecomputer happens to currently be executing, the priority encoder outputwill change to reflect the unique interrupt vector of the higherpriority interrupt. This new interrupt vector will be compared with thecurrent output of the status stack. The interrupt vector value (V) willbe greater than the status stack output (S), which will cause the newinterrupt vector (corresponding to the newly asserted external interruptinput) to be stored on the status stack. The computer will then beforced to execute the interrupt service routine for the newly assertedinterrupt input.

The two mask registers can be programmed one at a time by programsoftware. The registers are programmed in the same way as the externaldata RAM. The destination address of the mask register of interest isput in the Z field of the program word. The opcode and X and Y fields ofthe same program word are chosen such that the desired mask registercontents will appear on DZL1 when the mask register address appears onthe AZL2 address bus. The mask registers are memory-mapped within theASIC20 address space. The addresses of the two mask registers are shownin Table 1.

One or more interrupts can be disabled as directed by the software. All23 external interrupts can be masked by writing a 12-bit value to thetwo mask registers. To enable a certain interrupt, the programmer mustwrite a "1" to the corresponding bit in one of the two mask registers.The MSB of one of the mask registers will totally disable all 23interrupt inputs if it is set to a "1". If it is set to a "0", the 23interrupt inputs will be enabled or disabled according to the way theremaining bits in the mask registers are set. This MSB is known as theglobal enable bit. The second MSB of one of the mask registers enablesor disables the highest priority interrupt. The LSB of the other maskregister enables or disables the lowest priority interrupt input. Theremaining interrupt inputs are enabled or disabled by the remaining maskregister bits, with descending interrupt priority. The polarity of theindividual interrupt-enable bits is opposite to the polarity of theglobal interrupt-inhibit bit. If an interrupt control bit is a "1", thecorresponding interrupt will be enabled. If an interrupt control bit isa "0", the corresponding interrupt will be disabled.

Errant software may cause both the interrupt processor status stack andthe program stack to underflow by executing too may RET or RETIinstructions. Additionaly, more than 64 return addresses generated byCALL instructions will cause the program stack pointer to overflow.

The interrupt processor can be inhibited in three ways:

a. Hardware-initiated interrupt inhibit

b. Software-initiated interrupt inhibit

c. Global hardware inhibit during power-up

The hardware-initiated interrupt disable results when the MSB of theinstruction word is asserted. The MSB of the instruction word isasserted if a branch instruction has been output from the program PROM,of if a reference to any of the indirect addressing registers (containedelsewhere within the ASIC 20) exists in an instruction word. Due to thearchitecture of this ASIC 20, conditional branch instructions cannot beinterrupted.

The software program can disable the interrupt processor 44 by settingthe MSB of the second mask register at RAM address 0012AH. Both maskregister are only 12 bits wide. If the MSB of the second mask registeris a "1", all interrupts are disabled. This has been explained earlier.

The software can also disable the interrupt processor 44 using the resetinterrupt processor (RI) instruction. The RI instruction will reset theinterrupt processor by resetting the interrupt processor status stackand clearing all the interrupt input latches.

Finally, it is desirable to disable the interrupt processor 44 whenpower is first applied to the ASIC 20. This operation gives the ASIC 20a chance to execute initializing and "housekeeping" software beforebeing bothered by any interrupts. When power is applied to the ASIC 20,a power-up reset signal is applied to various locations in themicroprocessor 20. The power-up reset signal will clear the maskregisters, all interrupt input latches, and the interrupt status stack.

Important outputs of the interrupt processor can be monitored by theprogram software. This monitoring function is accomplished by tristatingthese outputs onto the 16-bit readability bus. Each of the followingoutputs of the interrupt processor preferably are memory-mapped withinthe ASIC20 internal-register address space:

a. Mask register 1;

b. Mask register 2;

c. Interrupt address RAM output;

d. Status stack output; and

e. Trap-address register output.

To determine the value of a desired interrupt processor output, theprogram software must contain an instruction whose AX source addresscorresponds to the desired output. An AX decode circuit will enable thecorrect tristate driver, causing the output of interest to appear on the16-bit readability bus. The value of the selected interrupt processoroutput will appear on the DZL1 data output bus two instruction cycleslater.

The overall operation of the ASIC 20 is shown by the general processtiming diagram of FIG. 7. FIG. 7 illustrates the output of someimportant signal nodes in the ASIC 20.

There are two ways of viewing the timing diagram. The first is to followa process number and see what happens to it during consecutive clockcycles. The second way is to observe all the events happeningsimultaneously during any one clock cycle. Both methods of explanationwill be used herein.

At the clock cycle (t-1), process no. 1 is generated at the output ofthe program counter 34 and (after some PROM access time) is realized asan instruction word at the output of the program PROM 36. Any X and

Y operands required for process no. 1 are fetched during the second halfof time t(-1).

At time t, process no. 1 is clocked into an instruction register. Ifprocess no. 1 is a computational instruction (arithmetic or a logical),the proper computation is executed using a value stored in the operandregister.

At time t+1, the result of the process no. 1 computation (appearing onDZL1 Data Bus) is written to a destination address during the positivephase of the clock cycle. Therefore, two and one-half clock cycles arerequired from the formulation of an instruction to its completion. Thedestination could be internal of external RAM, output, ports, internaltimers or latches, or the internal mask registers.

The following description uses the second method viewing the timingdiagram. Note that during any one clock cycle, four events are happeningsimultaneously. For explanation purposes, assume the current clock cycleis at time t.

First of all, the next instruction is generated by the program counter34 to generate a new address for the external program PROM 36. Theprogram PROM 36 outputs the instructions (after some access time delay)to be executed at the beginning of the next clock cycle, t+1.

Secondly, the instruction register has just clocked in and commencedexecution of the current instruction. This current instruction had beenprefetched from program PROM 36 during the previous (t-1) clock cycle.The current instruction being executed uses the operands clocked intothe operand register. These operands have also been prefetched duringthe second half of the previous clock cycle (t-1) by controlling anoperand select MUX (not shown) in the mathematical computation circuitryand multiplexing circuitry 40 to channel the correct operands into theoperand register. The third simultaneous event during the present clockcycle is writing the results (appearing on the DZL1 Data Bus) of theprevious phase of the current clock cycle. The DZL1 Data Bus is theinput of the RAMs, and the AZL2 address bus is multiplexed (with eitherthe AX or AY address buses) to the address ports of the internal RAM.Both the AZL2 address and DZL1 data buses were latched at the end of theprevious clock cycle to make stable data available to the RAM forwriting during the current clock cycle.

The fourth simultaneous event to happen is prefetching of the operandsfor the next instruction. Remember that next instruction has just beengenerated during this same clock cycle. During the negative phase of thecurrent clock cycle (t), the X and Y address buses are applied to theirrespective RAM address ports. The operand select MUX is controlled tochannel the proper source of the opernads to the input of the operandregister. The instruction register will clock in these operands upon therising edge of the next clock cycle (t+1).

The following table summarizes the instruction set of the ASIC 20. Theleft column is the digital code, and the right column is the mnemonic.

    ______________________________________                                        Instruction                                                                   Opcode              Mnemonic                                                  ______________________________________                                        1 000 00 0000       >=0     CALL                                              1 000 00 0001       >=0     JMP                                               1 000 00 0010       >=0     RET                                               1 000 00 0011       >=0     RETl                                              1 000 00 0100       <0      CALL                                              1 000 00 0101       <0      JMP                                               1 000 00 0110       <0      RET                                               1 000 00 0111       <0      RETl                                              1 000 00 1000       =0      CALL                                              1 000 00 1001       =0      JMP                                               1 000 00 1010       =0      RET                                               1 000 00 1011       =0      RETl                                              1 000 00 1100       NEO     CALL                                              1 000 00 1101       NEO     JMP                                               1 000 00 1110       NEO     RET                                               1 000 00 1111       NEO     RETl                                              1 000 01 0000       OVF     CALL                                              1 000 01 0001       OVF     JMP                                               1 000 01 0010       OVF     RET                                               1 000 01 0011       OVF     RETl                                              1 000 01 0100       CALL                                                      1 000 01 0101       JMP                                                       1 000 01 0110       RET                                                       1 000 01 0111       RETl                                                      0 lll 01 1000       Z = &X/&Y                                                 0 lll 01 1001       Z = X/&Y                                                  0 lll 01 1010       Z = &X/Y                                                  0 lll 01 1011       Z = X/Y                                                   0 lll 01 1100       Z = &X*&Y                                                 0 lll 01 1101       Z = X*&Y                                                  0 lll 01 1110       Z = &X*Y                                                  0 lll 01 1111       Z = X*Y                                                   0 lll 10 0000       Z = &X+&Y                                                 0 lll 10 0001       Z = X+&Y                                                  0 lll 10 0010       Z = &X+Y                                                  0 lll 10 0011       Z = X+Y                                                   0 lll 10 0100       Z = &X-&Y                                                 0 lll 10 0101       Z = X-&Y                                                  0 lll 10 0110       Z = &X-Y                                                  0 lll 10 0111       Z = X-Y                                                   0 lll 10 1000       Z = &X OR &Y                                              0 lll 10 1001       Z = X OR &Y                                               0 lll 10 1010       Z = &X OR Y                                               0 lll 10 1011       Z = X OR Y                                                0 lll 10 1100       Z = &X XOR &Y                                             0 lll 10 1101       Z = X XOR &Y                                              0 lll 10 1110       Z = &X XOR Y                                              0 lll 10 1111       Z = X XOR Y                                               0 lll 11 0000       Z = &X AND &Y                                             0 lll 11 0001       Z = X AND &Y                                              0 lll 11 0010       Z = &X AND Y                                              0 lll 11 0011       Z = X AND Y                                               0 lll 11 0100       Z = &X/2.sup.n                                            0 lll 11 0101       Z = X/2.sup.n                                             0 lll 11 0110       Z = SQRT(&X)                                              0 lll 11 0111       Z = SQRT(X)                                               0 lll 11 1000       Z = &X &Y                                                 0 lll 11 1001       Z = X &Y                                                  0 lll 11 1010       Z = &X Y                                                  0 lll 11 1011       Z = X Y                                                   0 lll 11 1100       Z = NOT(&X)                                               0 lll 11 1101       Z = NOT(X)                                                0 000 11 1110       Z = Rl                                                    0 000 11 1111       Z = RSP                                                   ______________________________________                                         NOTE:                                                                         l= 1 or 0 depending upon whether programmer wants the internal indirect       address registers (R.sub.x, R.sub.y, R.sub.z) to be used as source            operands or destination.                                                 

The ASIC 20 preferably has a 48-bit word length. The instruction setincludes five different types of instructions: arithmetic group, logicalgroup, branch group, miscellaneous group and indirect group. The twooperands for each type of arithmetic or logical instruction canoriginate from program PROM 36 or memory as X or Y, or from registers asR_(x) or R_(y). The arithmetic group of instructions includes add,subtract, multiply, divide and square root. The logical group ofinstructions includes AND, OR, EXCLUSIVE OR, and shift right. The branchgroup includes conditional and unconditional jump instructions,subroutine calls, returns from subroutine calls, and returns frominterrupt instructions. The miscellaneous group includes reset stackpointer (RSP) and reset interrupt processor (RI).

Indirect operations can be performed on all the arithmetic and logicalfunctions using any or all of three internal address registers (R_(x),R_(y), R_(z)). For example, an indirect Z=X+Y would add R_(x) and R_(y)together. A direct Z=X+Y would add the X and Y fields from the programROM together.

An instruction word may include bits identified as follows:

    ______________________________________                                        D       actual data from program ROM;                                         DI      disable interrupt;                                                    I       indirect operation using R.sub.x, R.sub.y, R.sub.z,                   R.sub.x, R.sub.y, R.sub.z                                                             operand registers of indirect instructions;                           S       a location for external data RAM, ROM or input                                ports;                                                                X       first source/data field;                                              Y       second source/data field;                                             Z       third field (for resulting data storage);                             &       actual data from program ROM on address                                       register; and                                                         !       used only in conjunction with the address                                     registers. Denotes the address registers used                                 as a memory address.                                                  ______________________________________                                    

A word may be formed with the bits having the following allocations:

    __________________________________________________________________________                         Operands Destination                                     Dl     R.sub.x                                                                          R.sub.y                                                                         R.sub.z                                                                          Instruction                                                                         X    Y   Z                                               __________________________________________________________________________    Bit field                                                                          47                                                                              46 45                                                                              44 43-48 37-22                                                                              21-11                                                                             10-0                                            __________________________________________________________________________

When DI=0 in bit 47, an interrupt will be allowed to occur. DI=1 doesnot allow an interrupt to occur. Bits 46- 44 are indirect registers withactive high. Bits 42-38 specify the instruction. For example, 100000 isZ=&X+&Y; 100001 is Z=X+&Y; 100010 is Z=&X+Y; and 100011 is Z=X+&Y;100010 is Z=&X+Y; and 100011 is Z=X+Y. The next 16 bits of the word,which are bits 37-22, contain the X operand, and bits 21-11 contain theY operand. The last 11 bits contain the location Z of the result of theinstruction operating on the operand.

For NOT and SQRT operations the word may be formed as:

    __________________________________________________________________________    Dl     R.sub.x                                                                         R.sub.y                                                                         R.sub.z                                                                          Instruction                                                                         Operand                                                                            11 zeros                                                                           Destination                                     __________________________________________________________________________    Bit field                                                                          47                                                                              46                                                                              45                                                                              44 43-48 37-22                                                                              21-11                                                                              10-0                                            __________________________________________________________________________

The word for NOT and SQRT has only an X operand. When bits 43-48 are111101, the instruction is Z=NOT(X); and 111100 is Z=NOT (&X).

For branch operations, including, including Return From Interrupt, theword may be formed as:

    __________________________________________________________________________    Dl     R.sub.x                                                                         R.sub.y                                                                         R.sub.z                                                                          Instruction                                                                         14 zeros                                                                           Destination                                                                         11 zeroes                                      __________________________________________________________________________    Bit field                                                                          47                                                                              46                                                                              45                                                                              44 43-48 37-24                                                                              23-11 10-0.                                          __________________________________________________________________________

Interrupts will not be allowed to occur when a branch instruction isbeing executed. Therefore DI=1 for all branch instructions. Bits 46-44will all be zeros because not indirect operations are allowed in thebranch instructions. Bits 43-38 specify the instruction. For example,000000 is Call >=0; 000001 is JMP>=0; 00010 is RET>=0; and 000011 isRETI>=0. Bits 23-11 specify the branch location applicable only to calland jump. Bits 37-24 and bits 10-0 are all zeros because these bits arenot used by branch instructions.

For miscellaneous instructions (RSP and RI) the word may be formed as:

    ______________________________________                                               Dl  R.sub.x R.sub.y                                                                             R.sub.z                                                                             Instruction                                                                           38 zeros                               ______________________________________                                        Bit field                                                                              47    46      45  44    43-48   37-0                                 ______________________________________                                    

Interrupts will not be allowed to occur when an RSP or RI is beingexecuted. Therefore DI=1 for all branch instructions. Bits 46-44 arezero because no indirect registers are used with RSP or RI instructions.Bits 43-38 specify the instruction; for example, 111111 is RSP; and111110 is RI. The remaining bits are zero becauses they are not used byeither RSP or RI.

The structures and methods disclosed herein illustrate the principles ofthe present invention. The invention may be embodied in other specificforms without departing from its spirit or essential characteristics.The described embodiments are to to be considered in all respects asexemplary and illustrative rather than restrictive. Therefore, theappended claims rather than the foregoing description define the scopeof the invention. All modifications to the embodiments described hereinthat come within the meaning and range of equivalence of the claims areembraced within the scope of the invention.

What is claimed is:
 1. An integrated circuit chip for application in a computer for performing high speed arithmetic operations in hardware, comprising:a system clock processor circuit formed in the chip; a timer circuit formed in the chip and connected to the system clock processor to receive clock signals therefrom; a program counter and branching circuit formed in the chip and connected to the system clock processor to receive clock signals therefrom; an interrupt processor circuit formed in the chip and connected to the program counter and branching circuit and to the system clock processor circuit to receive signals therefrom; an interrupt address random access memory connected to the interrupt processor to receive an interrupt vector signal therefrom; mathematical computation circuitry formed in the chip and connected to receive timing signals from the system clock processor and the timing circuit, and for performing instruction look-ahead to permit execution in one clock cycle, and connected to the timing circuit, the interrupt processor and the program counter and branching circuit to provide data thereto; and an internal data random access memory formed in the chip and connected to the mathematical computation circuitry and the interrupt address random access memory to exchange instructions and data therewith.
 2. The integrated circuit chip of claim 1 wherein the mathematical computation circuitry includes a circuit for performing combined division and square root operations.
 3. The integrated circuit chip of claim 2 wherein the circuit for performing combined division and square root operations includes:means for processing a 32-bit numerator and a 16-bit denominator; means for performing square root operations on a 16-bit radicand; and a 32-bit barrel shifter.
 4. The integrated circuit chip of claim 1 including a fixed instruction set.
 5. The integrated circuit chip of claim 4 further including means for executing each instruction in a single clock cycle.
 6. The integrated circuit chip of claim 5 further including means for performing 16×16-bit multiplication to produce a 32 bit output. 